1. Field of the Invention
The present invention relates to methods for production of semiconductor devices, and more specifically to an improvement applicable to methods for production of buried insulating layers each of which surrounds a portion of a semiconductor substrate in which elements are fabricated, the buried insulating layers functioning to isolate from one another, each element fabricated in a chip.
2. Description of the Prior Art
There is now a tendency in which the dimensions of each element is decreased in order to satisfy requirements for a larger quantity of elements fabricated in a chip and also for a larger quantity of elements fabricated in the unit area of a chip. Such requirements are included in the requirements effective to satisfy the ultimate purposes for development of LSI's and further of VLSI's. Insofar as the processes for isolating each element fabricated in one chip from one another are concerned, a process which is called local oxidation of silicon is available, and it is well known that this process has various advantages in the aspects of easy production of durable wiring which is free from potential discontinuation thereof and the potential employment of self-alignment and the like. However, this local oxidation process has drawbacks. The first is the problem of bird's beak. Referring to FIG. 1, local oxidation of the top surface of a silicon (Si) substrate 11, having a limited area covered by a silicon nitride (Si.sub.3 N.sub.4) layer mask 12, is accompanied by lateral growth of a silicon dioxide (SiO.sub.2) layer 13. This lateral growth produces a silicon dioxide (SiO.sub.2) layer having a bird's beak shape which extends under the silicon nitride (Si.sub.3 N.sub.4) layer 12. The lateral length A of this bird's beak causes a degradation of dimensional accuracy. The second is the problem of strain which is produced in the portion B of the silicon substrate 11. The portion B directly contacts the layer 13 of silicon dioxide (SiO.sub.2) which is converted from silicon (Si) during the oxidation process which inevitably causes expansion in volume of the nitride. This strain, appearing in the silicon (Si) layer B, can cause unsatisfactory characteristics in elements fabricated in the silicon (Si) layer. The third is the problem of white ribbon. Since it is not easy to completely remove the silicon nitride (Si.sub.3 N.sub.4) layer 12, numerous minute particles of the nitride remain on the surface of the silicon (Si) substrate 11 in the form of scattered stains. These residual nitride particles function as a type of mask during oxidation processes carried out in later steps.
The above process results in a local oxidation process which is not necessarily satisfactory for the production of a semiconductor device having minute patterns. To overcome the foregoing drawbacks, a method wherein each element is isolated from one another by buried insulating layers which are grown to fill grooves produced along the surface of a silicon (Si) substrate to surround each element, has been developed and is presently being used. Unfortunately, however, this improved method has other drawbacks described below, with reference to the drawings.
Depending on the etching process employed, this improved prior art method is classified into two independent categories.
The first is the case wherein a dry etching process is employed. Referring to FIG. 2(a), the first step is to employ a chemical vapor deposition process for the purpose of growing an insulating layer 22 on a silicon (Si) substrate 21 which is provided with grooves 23 surrounding mesa shaped portions 24 in which elements are to be fabricated, before a photoresist layer 25 is coated on the uneven surface of the insulating layer 22. As a result, the top surface of the photoresist layer 25 becomes flat. Referring to FIG. 2(b), the second step is to employ a dry etching process which has a single etching rate regardless of the quality of the material to be etched, to the substrate 21 covered by the insulating layer 22 and by the photoresist layer 25. As a result, the insulating layer 22 remains only in the groove 23, and the top surface of the silicon (Si) substrate 21 becomes uncovered. During this process, however, the ion beams employed for the dry etching process readily produce damaged areas C along the top surface of the mesa shaped portion 24 of the silicon (Si) substrate 21 in which elements are to be fabricated. These damaged areas can cause unsatisfactory characteristics for elements fabricated in the substrate 21. It is quite natural that the silicon (Si) substrate must be exposed to a plurality of high temperature processes such as oxidation and annealing for repairing the damage caused by application of ion implantation processes and the like, during later processes for production of elements therein. Referring to FIG. 2(c), since the foregoing high temperature processes are involved with non-uniform variation of density of the insulating layer 22, this variation causes strains E.sub.1 and/or E.sub.2 to occur at the corners of the mesa shaped portion 24 of the substrate 21 surrounded by the buried insulating layer 22. These strains are also parameters for causing unsatisfactory characteristics for elements fabricated in the substrate 21.
The second is the case wherein a wet etching process is employed. Referring to FIG. 2(d), the first step is to employ a dry etching process to remove the photoresist layer 25 from the areas on which elements are to be fabricated, leaving the photoresist layer 25 only along the grooves. Referring to FIG. 2(e), the second step is to employ a wet etching process to remove the insulating layer 22 from the areas on which elements are to be fabricated, leaving the insulating layer 22 only in the grooves 23. Since the grooves 23 have sharp corners at the bottom and top edges, the density of the insulating layer 22 is not entirely uniform and the density thereof is less along the broken lines shown in each of FIGS. 2(a), 2(b), 2(d) and 2(e) than in the other regions. Since a material having a lower density has a larger etching rate, recesses D are produced along the edges of the insulating layers 22 which are buried in the silicon (Si) substrate 21. As a result, the surface of a chip is not flat, causing the possibility of discontinuity and/or dimensional errors for wires which are placed along the silicon (Si) substrate 21.
To prevent occurrence of the foregoing recesses D along the edges of the insulating layer 22, an annealing process is ordinarily employed after the completion of the insulating layer 22. Albeit this annealing process is effective to unify or make uniform the density of the insulating layer 22 even in the portions along the broken lines shown in FIG. 2, differences in the amount of the coefficient of expansion between the material of the substrate and the material of the insulating layer causes stresses to occur along the interfaces of both materials, since the stresses are concentrated along the edges. As a result, strains E.sub.1 and/or E.sub.2 occur along the edges of the element fabrication areas of the substrate 21 surrounded by the buried insulating layer 22 in FIG. 2(f). These strains are also parameters for causing unsatisfactory characteristics for elements fabricated in the substrate 21.